Display devices may be constructed with a timing controller (TCON) that sends high rate (e.g., video) data to driver integrated circuits (DICs) on source boards at the display panel. In addition to the video data sent in the “forward” direction, reverse data may also be sent by the DICs to the TCON. Such reverse data may carry information, for example, from sensors (e.g., touch sensors or optical sensors) embedded in the display panel. The data rate of the reverse data may be lower than (e.g., 1/10th) that of the forward data.
The use of the individual forward links as bi-directional links, e.g., in a full-duplex or half-duplex system, may result in near end crosstalk (NEXT) for the forward link and vice versa. The use of dedicated reverse lanes (one per DIC) may result in a need to add traces, connectors, and cables to the system, and may consequently increase cost. The additional of a chip to the source board that aggregates the data from all low-speed reverse links and sends the aggregated data back to the TCON at high speed may also increase cost, and complexity.
Thus, there is a need for a cost-effective system for transmitting reverse data from a plurality of DICs to a TCON.